Published in Nature Journal
Solving the Capacity-Power Efficiency Trade-off
Enhancing Power Efficiency in Data Centers and Beyond
Researchers at Samsung Electronics have succeeded in developing a next-generation ferroelectric-based NAND flash technology that reduces power consumption by up to 96%. As the demand for high-capacity and high-efficiency storage grows with the proliferation of artificial intelligence (AI), this breakthrough is being hailed as a fundamental technology capable of overcoming the power consumption limitations of existing architectures.
On November 27, Samsung Advanced Institute of Technology (SAIT) announced that it has confirmed the potential to reduce power consumption by up to 96% during cell string (serial cell structure) operation, compared to conventional NAND flash, by introducing a new NAND flash structure that combines oxide semiconductors and ferroelectrics. A total of 34 researchers from SAIT and the Semiconductor Research Institute jointly participated in this study. The research results were published in the world-renowned journal Nature under the title "Ferroelectric transistors for low-power NAND flash memory."
Conventional NAND flash stores data by injecting electrons into cells. However, increasing the number of stacked layers to expand capacity leads to higher power consumption during read and write operations. While next-generation ferroelectric-based NAND technologies have been proposed multiple times, the trade-off between increased capacity and reduced power efficiency has remained an unresolved challenge.
The Samsung Electronics research team found a breakthrough in the properties of oxide semiconductors. They discovered that characteristics previously considered a weakness in high-performance devices-due to the limitations of threshold voltage control (the voltage at which a transistor begins to turn on)-actually serve to significantly reduce power consumption in ferroelectric-based structures.
Leveraging this property, the researchers became the first in the world to demonstrate a mechanism that dramatically reduces power consumption while maintaining high capacity of 5 bits per cell. This achievement overturns the technical limitations of conventional NAND flash structures through a novel approach to materials and architecture.
If commercialized, this technology is expected to greatly enhance power efficiency across a wide range of applications, including AI data centers and mobile and edge AI devices. Data centers can expect reduced operating costs, while mobile devices could see extended battery life.
Yoo Sijeong, the first author of the study and a researcher at Samsung Electronics SAIT, stated, "I am proud to have confirmed the feasibility of ultra-low-power NAND flash. As the role of storage in the AI ecosystem continues to grow, we will pursue further research with the goal of commercializing this technology in future products."
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