[Chip Talk] Jensen Huang's Unwavering Trust... TSMC Maintains Its Lead in Advanced Packaging

Jensen Huang: "No Alternative to TSMC Packaging"
TSMC Leads Packaging Market with Foundry Dominance
Samsung in Pursuit, but Securing Clients Remains Challenging
TSMC Unveils Next-Generation Technology That Bypasses Substrates

"At present, there is no practical alternative to CoWoS (Chip on Wafer Substrate)."

Jensen Huang, CEO of Nvidia, is answering questions at the GTC Taipei Global Press Conference held in Taiwan on the 21st of last month. Photo by AFP

Nvidia CEO Jensen Huang made this statement at the GTC Taipei Global Press Conference held in Taiwan on May 21. He was responding to a question about the growing importance of advanced packaging technology and how Samsung and Intel's technologies compare. 'CoWoS' is an advanced packaging method in which multiple chips are placed at very close intervals on a wafer and then reattached to a substrate. This is a proprietary technology of Taiwan's TSMC.

Because the distance for signal transmission between chips is extremely short, data transfer speeds are dramatically increased. In addition, GPUs and high-bandwidth memory (HBM) can be placed closer together, making this technology essential for maximizing the performance of artificial intelligence (AI) and high-performance computing (HPC). The latest chips are manufactured by combining multiple chips to maximize functionality. Nvidia's 'Blackwell,' which places a GPU and several HBMs on a single substrate, is an example of this approach.

◆Advanced packaging technology emerges as the 'core' in the AI era= In the past, semiconductor packaging simply referred to post-processing work that connects chips and ensures proper power delivery. Now, however, packaging has become a critical process that determines performance and efficiency depending on chip arrangement and configuration. This is especially true because it connects different types of chips, such as memory and system semiconductors, to ensure stable operation.

TSMC, the world's largest foundry (semiconductor contract manufacturing) company, also effectively dominates the advanced packaging market. Although it is difficult to confirm a separate market share, the fact that chips used by global big tech companies?such as Nvidia, AMD, Apple, Amazon, and Google?are all packaged using the CoWoS process demonstrates TSMC's overwhelming competitiveness. It is also reported that Nvidia has already secured packaging volume for AI chips to be supplied three years from now.

TSMC first introduced CoWoS technology in 2012 and began commercializing it in the HPC market the following year. Its customers include global big tech companies such as Nvidia, AMD, and Apple. Considering that Samsung Electronics unveiled its 2.5D packaging technology 'I-Cube' in 2018 and its 3D packaging method 'X-Cube' in 2020, TSMC was significantly ahead. Its robust foundry ecosystem is further strengthened by its technological capabilities and long-standing experience.

As the importance of HBM and other technologies grows in the AI chip era, the advanced packaging market is also expected to continue expanding. According to market research firm Yole Intelligence, the advanced packaging market?including 2.5D packaging?is projected to grow from $44.3 billion (about 61 trillion won) in 2022 to $78.6 billion (about 108 trillion won) in 2028. TSMC is increasing its CoWoS-based packaging revenue and plans to maintain an average annual growth rate of 50% going forward.

TSMC's 2.5D advanced packaging technology CoWoS. TSMC

Explanation of TSMC's recently unveiled ultra-large-scale high-density packaging technology 'SoW-X (System on Wafer-X)'. TSMC

◆TSMC's dominance continues, unveiling next-generation packaging= Although semiconductor companies such as Samsung Electronics are striving to develop advanced packaging processes, it is considered unlikely that they will be able to stop TSMC's dominance.

TSMC has even announced plans to introduce next-generation advanced packaging technology. TSMC recently unveiled its ultra-large-scale high-density packaging technology 'SoW-X (System on Wafer-X)'. Because semiconductors can develop cracks due to heat, the required technological capabilities vary depending on the size of the substrate. If the substrate area is increased indiscriminately, it leads to longer data travel distances, increased power loss, and performance degradation.

According to TSMC, SoW-X eliminates the need for a substrate altogether. This means that, in AI chip manufacturing, a silicon interposer connecting the chip and substrate is no longer required. By skipping this costly intermediate step, chips can be stably interconnected at the wafer level. TSMC aims to improve performance by up to 40 times compared to CoWoS and has announced plans to begin mass production in 2027.

TSMC's new factories in Arizona, USA, are also aligned with these plans. Two newly constructed packaging-only factories and a research and development (R&D) center to be established within the existing fab complex are seen as steps to solidify TSMC's market dominance through advanced packaging technology. However, this 'game changer' has yet to reveal details such as yield or unit price, which are expected to be very high.