Samsung Plants the HBM4 Flag First... World’s First Mass Shipments to Nvidia

Executive Vice President Hwang Sangjoon: "Meeting Demands for Higher Performance"
Operating Speeds Up to 13 Gbps
Cutting-Edge 1c DRAM and 4 nm Foundry Processes
HBM4E Sample Shipments Planned for the Second Half of This Year

Samsung Electronics has begun full-scale efforts to preempt the market by becoming the first in the world to mass-produce and ship sixth-generation High Bandwidth Memory (HBM4). It appears that deliveries to major customers such as Nvidia, which the industry had expected as early as the third week of this month, have started earlier than anticipated.

On the 12th, Hwang Sangjoon, Executive Vice President in charge of Memory Development at Samsung Electronics, stated in a press release, "Samsung Electronics' HBM4 broke with the precedent of applying only previously validated process nodes and instead adopted cutting-edge process technologies such as 1c DRAM and 4 nm foundry (1 nm = one-billionth of a meter)," adding, "By fully securing headroom for performance scaling through process competitiveness and design improvements, we were able to meet our customers' performance upgrade requirements in a timely manner."

The previous day, at the "Semicon Korea 2026" event, Song Jaehyuk, President and Chief Technology Officer (CTO) of the Device Solutions (DS) Division at Samsung Electronics, also expressed confidence regarding the news of HBM4 shipments, saying, "We are now showing you our true capabilities."

Samsung Electronics HBM4 product photo. Samsung Electronics.

Samsung Electronics explained that from the initial development phase of HBM4, it set performance targets exceeding the standards of the international industry standards organization JEDEC and pushed development forward accordingly. For this product, the company introduced cutting-edge 1c DRAM (10 nm-class sixth generation), securing stable yields and industry-leading performance from the early stage of mass production without any redesign.

To strengthen its HBM4 technology competitiveness, Samsung Electronics applied 1c DRAM and, taking into account the characteristics of the base die, adopted a 4 nm process that is advantageous in terms of performance and power efficiency. As a result, Samsung Electronics' HBM4 has stably achieved an operating speed of 11.7 Gbps, which is approximately 46% higher than the JEDEC industry standard of 8 Gbps. This represents about a 1.22-fold improvement compared with the maximum pin speed of 9.6 Gbps for the previous HBM3E, and it can scale up to 13 Gbps. It is therefore expected to effectively alleviate the data bottlenecks that intensify as artificial intelligence (AI) model sizes grow.

The company also stated that it has increased total memory bandwidth per single stack to up to 3.3 TB/s, about 2.7 times higher than that of the previous HBM3E, thereby achieving performance that exceeds the 3.0 TB/s level demanded by customers.

Samsung Electronics' HBM4 provides a capacity of 24 to 36 GB through 12-high stacking technology, and the company plans to expand capacity to up to 48 GB by applying 16-high stacking technology in line with customers' product schedules.

As the number of data input/output (I/O) pins for data transfer has increased from 1,024 to 2,048, Samsung Electronics applied low-power design technology to the core die to address the resulting power consumption and heat concentration issues. In addition, by applying low-voltage design technology for silicon via (TSV) data transmission and reception and optimizing the power delivery network (PDN), the company improved energy efficiency by about 40% compared with the previous generation, while enhancing thermal resistance characteristics by about 10% and heat dissipation characteristics by about 30%.

Samsung Electronics is an integrated device manufacturer (IDM) capable of providing a "one-stop solution" that spans logic, memory, foundry (semiconductor contract manufacturing), and packaging. As HBM becomes more advanced, the role of the base die is expected to grow even more important. Samsung Electronics plans to continue developing HBM through close design-technology co-optimization (DTCO) between its in-house foundry processes and HBM design.

The company also explained that, by possessing advanced packaging capabilities in-house, it can minimize supply chain risks while securing competitiveness in shortening production lead times. At the same time, Samsung Electronics has been continuously receiving requests for HBM supply partnerships from major global graphics processing unit (GPU) makers and next-generation application-specific integrated circuit (ASIC)-based hyperscaler customers that design and develop their own chips, and it plans to further expand technological collaboration with these customers.

Against this market backdrop, the company expects its HBM revenue in 2026 to more than triple compared with 2025 and is preemptively expanding its HBM4 production capacity. The company also stated that, based on its industry-leading DRAM production capacity and the cleanroom infrastructure it has secured through proactive investments, it has the production flexibility to respond swiftly even if HBM demand surges.

In addition, the Pyeongtaek Campus Phase 2 Line 5, which will enter full-scale operation from 2028, is slated to serve as a core hub for HBM production. The company plans to continuously secure stable supply response capabilities even amid a mid- to long-term phase of demand expansion centered on AI and data centers.

Following HBM4, Samsung Electronics is also preparing HBM4E and plans to begin sample shipments in the second half of this year. The company also plans to start sequential sampling of custom HBM tailored to each customer's requirements from 2027.