HBM4, 66% Bandwidth Improvement Target
Data Transfer Speed Innovation with CXL Technology
Samsung Electronics is gearing up to develop next-generation semiconductor technologies to usher in a new half-century. In particular, it is aiming to take the lead in next-generation semiconductor technologies such as HBM4, the 6th generation High Bandwidth Memory (HBM), and Compute Express Link (CXL). These are all core technologies gaining attention in the fields of artificial intelligence (AI) and high-performance computing (HPC).
◆ Memory and R&D Combined for a ‘Speed Race’= HBM, directly overseen by Samsung Electronics Vice Chairman Jeon Young-hyun, is strengthening its research and development efforts. The company is preparing for the development and mass production of HBM4, targeting the second half of next year. It is currently in the ‘pilot production’ phase, building a dedicated HBM4 line called ‘D1c’ and producing small-scale trial products.
Earlier this year, Samsung Electronics unveiled the specifications of HBM4 at the semiconductor academic conference ‘ISSCC 2024.’ Compared to the previous generation HBM3E, it plans to improve bandwidth (memory data transfer speed) by 66%, and power efficiency and capacity by 33% each. The number of data input/output ports will be doubled to increase the transfer speed per port, and a 16-layer stacked structure will provide a capacity of 48GB. The device structure of the buffer die, which is the chip at the bottom of the HBM that exchanges data with the outside, will transition from the existing planar transistor to a FinFET structure. The FinFET structure is a three-dimensional design that increases the contact area between the gate and channel, allowing more precise control of current flow and reducing power consumption.
Except for the buffer die, the other stacked core chips, called core dies (which store and process data), adopt the 1c DRAM process. This skips the 1b process used by competitors SK Hynix and Micron and goes straight to 1c. The 1c process is a finer process technology than the previous generation (1b process), with higher transistor and cell density, enabling more data storage in the same area. However, because the 1c process is finer than 1b, securing yield is more difficult and there are higher risks in the initial production phase. Nevertheless, choosing 1c reflects a determination to technologically surpass competitors.
To enhance the performance and stability of HBM4, Samsung is also preparing Non-conductive Film (NCF) assembly technology optimized for high-temperature thermal characteristics and Hybrid Copper Bonding (HCB) technology. These are important semiconductor packaging technologies that improve performance, reliability, and stability in stacked memory structures like HBM. NCF assembly technology is an adhesive technique that securely bonds chips and prevents electrical signal interference even in high-temperature environments, while HCB technology is an advanced bonding method using copper bonding to speed up data transfer and reduce heat generation.
◆ CXL, the Core of Next-Generation Memory= CXL is also expected to be a ‘super-gap’ technology that Samsung Electronics will showcase in the future. CXL is a next-generation interface technology that enables faster and more efficient data transfer among computer components such as CPUs, memory, and GPUs. Samsung Electronics developed the industry’s first CXL-based DRAM in 2021 and has continuously introduced related products since then.
The CXL market is expected to fully open within the next one to two years. Last year, Samsung developed the CXL 2.0 version, and it is anticipated that the CXL 3.1 version will be introduced in 2026. Controllers and switches supporting CXL 3.1 are expected to be completed, and CPUs supporting this will likely be released at that time.
Market research firm Yole Intelligence projected that the CXL market size will grow from about $1.7 million (approximately 2.4 billion KRW) in 2022 to $15 billion (approximately 21 trillion KRW) by 2028.
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