[Peace&Chips] 'Hybrid Bonding' Leading the Next Generation of HBM

Technology for Heterogeneous 3D Packaging Implementation
Connecting Chip Surfaces with Copper to Enhance Performance and Quality
Key Front-End Process Technology... Essential for Next-Generation HBM

Editor's NoteSemiconductors, known as the rice of modern industry. Although it's a term we hear every day, it's often hard to explain. Peace & Chips will make the complex concepts and overall flow of the semiconductor industry easy to digest for you. Just bring your spoon.

[Peace&Chips] 'Hybrid Bonding' Leading the Next Generation of HBM

Recently, when reading semiconductor articles, the word 'packaging' can be found quite easily. As the semiconductor industry faces limits in improving performance due to the constraints of advanced process technology despite massive investments, attention is turning to packaging.

Packaging, as mentioned in the industry, refers to the concept of bundling multiple semiconductor chips to maximize performance. Packaging has evolved from 2.5D, where chips are arranged with logic laid out horizontally and memory stacked vertically, to 3D integration where chips are stacked entirely vertically. Particularly, heterogeneous integration using 3D packaging, where different chips function as one semiconductor, is gaining attention.

The technology required here is called 'Hybrid Bonding.' To stack chips, multiple spherical conductive bumps that allow electricity to pass between chips are usually needed, but hybrid bonding eliminates these bumps and bonds the chips directly. Utilizing the space freed by removing bumps can improve performance and quality. It can also reduce the size of packaged products.

Bump image used when placing chips. The core of hybrid bonding technology is to eliminate these bumps. / [Image source=Samsung Semiconductor Newsroom content capture]

The principle of bonding chips is as follows. The chip surface has copper (Cu) and oxide film (SiO2); copper bonds with copper, and oxide film bonds with oxide film through heat treatment. Since it bonds two different materials, it is called hybrid bonding. Although it may seem simple, flattening the chip surface is not easy, and the heat treatment process is technically challenging.

An interesting point is that hybrid bonding uses front-end process technology. The front-end process refers to a series of steps that draw circuits on a silicon wafer to complete the semiconductor chip base (die). The finishing process to complete the chip into a final product is called the back-end process.

Packaging is usually considered part of the back-end process, but in the case of hybrid bonding, since heterogeneous chip dies are bonded directly on the wafer, front-end process technology is crucial. This is also why Applied Materials, a leading company in front-end equipment, is interested in the packaging business. They are currently focusing on developing equipment for hybrid bonding.

An image explaining the hybrid bonding process divided into oxide height reduction technology (a) and copper dishing control technology (b). / [Image source: Excerpt from the paper 'Cu-SiO2 Hybrid Bonding']

Hybrid bonding is closely related to High Bandwidth Memory (HBM), a key keyword in the industry. HBM is a high-performance, high-capacity memory made by stacking multiple DRAM chips. Its demand is rapidly increasing due to its use in artificial intelligence (AI).

The industry expects the utilization of hybrid bonding to increase when producing next-generation HBM. As HBM performance improves, stacking height will continue to rise, so hybrid bonding is used to reduce product thickness. Applied Materials is collaborating with all manufacturers producing HBM to expand the application of hybrid bonding equipment. In the HBM market, Samsung Electronics and SK Hynix hold over 90% market share.