[Click eStock] Nepes, Positive Signals and a New Phase for Mid-to-Long-Term Directionality

[Asia Economy Reporter Lee Seon-ae] Hana Financial Investment evaluated on the 1st that the geopolitical status of Korean non-memory back-end process companies, including Nepes, is newly emerging.

Kim Kyung-min, a researcher at Hana Financial Investment, explained, "Non-memory semiconductor back-end packaging technology has developed mainly in the Greater China region, but due to ongoing trade disputes, global semiconductor design (fabless) clients are seeking ways to reduce their dependence on Greater China back-end packaging companies," adding, "Accordingly, the geopolitical status of Korean companies such as Nepes is newly emerging."

He continued, "Along with these changes, Samsung Electronics, which has been at the center of the Korean memory back-end ecosystem, is providing faster growth opportunities to outsourcing partners in the non-memory back-end service sector," and added, "The medium- to long-term direction of the external environment is judged to be positive for the Korean non-memory back-end industry."

However, no investment opinion or target price was presented for Nepes.

The packaging method of chips mounted on mobile devices is evolving into Advanced Packaging. In particular, the form factor of mobile devices has taken various shapes such as foldable, rollable, and wearable, which ultimately demands increased complexity in semiconductor back-end processes.

In the case of Nepes, together with its subsidiaries, it has advanced beyond traditional wafer-level packaging (WLP) through a technology called nPLP (Panel Level Packaging). To be more precise, nPLP is Fan-out nPLP. Unlike traditional wafer-level packaging (WLP), it has a wider redistribution layer area relative to the limited semiconductor (chip) size, making signal transmission more efficient. Nepes (including subsidiaries) has enlarged the panel size to 600mm x 600mm in Fan-out nPLP (panel level packaging) and provides a turnkey solution that includes not only packaging but also testing.

This technology is applied to the back-end process of PMIC (Power Management IC). So far, it is implemented as a single chip solution only for PMIC, but Nepes is pursuing diversification of applications by expanding from single chip solutions to multi-chip solutions including 3D packaging. Separately, Nepes is developing nSiP (Nepes System in Package) technology that does not require printed circuit boards (PCB) for packaging.