[ChipTalk] Next-Gen 'HBM4' Standardization Nears... Samsung Electronics vs TSMC·SK Hynix Alliance, Who Will Win?

JEDEC "Next-Generation Standard Nearing Completion"

SK Hynix Forms Alliance with Taiwan's TSMC
Samsung Electronics Strengthens 'Turnkey Strategy'

With the rapid growth of the artificial intelligence (AI) market, the next-generation product specification for HBM (High Bandwidth Memory), which is gaining attention, is expected to be announced by the end of this year at the latest. The competition for the 6th generation 'HBM4,' which will become a game changer in the HBM market starting next year, is set to intensify. As new technologies are introduced in product mass production and a large number of customer-tailored features are expected to be incorporated, the development competition among HBM companies to secure leadership is anticipated to become even fiercer. In particular, attention is focused on the competitive landscape between SK Hynix, a strong player in HBM that has partnered with Taiwan's TSMC, the world's No. 1 foundry (semiconductor contract manufacturing) company, and Samsung Electronics, which boasts the advantage of being a comprehensive semiconductor company engaged in both HBM and foundry businesses.

On the 22nd, the JEDEC Solid State Technology Association, an international semiconductor standards organization, recently announced that "the HBM4 standard is nearing completion." This is the first time JEDEC has announced the progress of the HBM4 standardization.

JEDEC is an organization composed of global semiconductor and tech companies. It gathers opinions from semiconductor companies and customers to create standard specifications for the entire semiconductor supply chain, including memory semiconductors such as DRAM and NAND flash, as well as interfaces and packaging. JEDEC standards can be seen as guidelines for designing and manufacturing new semiconductors. The completion of the standard marks the point at which full-scale HBM4 development becomes possible.

JEDEC has disclosed some of the specifications of HBM4, which is in the final stages of completion. The performance benchmarks are similar to those previously known. HBM4 supports up to 16 layers, a level higher than the 12 layers of HBM3 and HBM3E. This means that the capacity per unit area increases and the speed becomes faster. The capacity per DRAM also expands from the previous maximum of 24Gb (gigabits) to 32Gb. Not only does the number of layers increase, but the capacity density per layer also rises.

Additionally, the number of channels per layer, previously 1028 bits, doubles to 2048 bits, and it was confirmed that the semiconductor chip area is larger. The speed per channel has been initially agreed upon at 6.4Gbps (gigabits per second). This speed is likely to increase further, as the HBM3E currently supplied to the market supports 8Gbps.

However, JEDEC did not mention the stacking height. Originally, JEDEC planned to announce the HBM4 specifications earlier this year, but the announcement was delayed due to disagreements among member companies regarding the stacking height. JEDEC is reportedly trying to relax the height limit from the existing 720 micrometers (μm) to 775μm. More space is needed to stack a higher number of layers.

As the product specifications take shape, the memory industry is making even more thorough preparations for HBM4 mass production. The real battleground surrounding HBM will be HBM4. The 6th generation HBM4 requires a level of difficulty in design and manufacturing that is different from previous products.

NVIDIA, a key AI semiconductor customer, announced in its Computex keynote speech last June that it will first equip the 2026-released 'Rubin' platform with eight HBM4 units and the 2027 'Rubin Ultra' with twelve HBM4 units, according to its roadmap. AMD also plans to equip the 'MI400,' launching in 2026, with HBM4 for the first time.

SK Hynix, which has maintained HBM leadership, has decided to closely cooperate with Taiwan's TSMC to strengthen next-generation HBM production and advanced packaging technology capabilities. The two companies recently signed a memorandum of understanding (MOU) for technical cooperation in Taipei, Taiwan, with plans to develop HBM4.

Since companies with strengths in different fields have agreed to collaborate, they are showing confidence. SK Hynix recently announced that it will advance the mass production timing of HBM4 by about a year to 2025. This is interpreted as a strategy to meet the demands of major big tech companies and quickly secure customers.

The two companies will first work on improving the performance of the Base Die, which is mounted at the bottom of the HBM package. HBM is made by stacking Core Dies, which are individual DRAM chips, on top of the Base Die and vertically connecting them using TSV technology. The Base Die is connected to the GPU and controls the HBM.

SK Hynix produced the Base Die using its own process up to the 5th generation HBM3E, but plans to utilize advanced logic processes starting with HBM4. Applying ultra-fine processes to produce this die allows for the addition of various functions. Through this, the company plans to produce customized HBM that meets a wide range of customer demands, including performance and power efficiency. Additionally, SK Hynix and TSMC, who hold patents on the proprietary CoWoS process, have agreed to jointly respond to customer requests by combining their technologies.

Samsung Electronics plans to use HBM4 as an opportunity to reverse its position in the HBM market. Samsung Electronics owns both the System LSI division and the Foundry division, allowing it to work together from the initial design of the HBM4 Base Die to performance optimization. Chip manufacturers like NVIDIA prefer to entrust the entire process, including foundry and packaging, to a single company, so Samsung's so-called 'turnkey' strategy, which offers integrated production, can provide competitiveness in the bidding process.

In particular, Samsung's Non-Conductive Film (NCF) technology applied to HBM is considered optimal for HBM4, which increases the number of layers to 16, as it is advantageous for high stacking. Samsung is also accelerating the development of hybrid bonding technology that enables high stacking at lower heights. In April, Samsung announced that it had implemented 16-layer HBM4 using hybrid bonding.

Samsung Electronics recently expressed its intention to realize customer-tailored products starting with HBM4 through the 'Samsung Foundry Forum.' Samsung has proposed an 'AI solution' strategy that provides customers with HBM DRAM, foundry, and advanced packaging all at once.