[Peace&Chips] After NAND, stacking competition in DRAM... Samsung and Hynix increase HBM layer count

HBM Stacking DRAM in Four Layers
16-Layer HBM to Follow 12-Layer

Manufacturing Technology to Increase Stacking Layers Draws Attention
Competition Between Samsung Electronics and SK Hynix

Recently, a new stacking competition has been active in the memory semiconductor industry. Previously, stacking competition was prominent in the NAND flash sector, but now attempts to increase the number of layers are also rising in the DRAM field. This is due to the rapidly growing demand for high-bandwidth memory (HBM) used for artificial intelligence (AI) memory.

HBM is a type of high-performance DRAM that stacks multiple DRAM chips vertically and connects them to increase data processing speed. Since its first development in 2013, it has evolved through the 1st generation (HBM), 2nd generation (HBM2), 3rd generation (HBM2E), 4th generation (HBM3), and 5th generation (HBM3E). Currently, there is even an HBM3E 12-layer product that stacks 12 individual DRAM chips.

The memory industry has been enhancing HBM technology while increasing the number of layers in products. They have increased capacity by stacking in increments of four layers: 4-layer, 8-layer, and 12-layer products. This is because the HBM standards set by the JEDEC (Joint Electron Device Engineering Council) require stacking in multiples of four layers.

The latest product, HBM3E, has been released in 8-layer and 12-layer versions. As we enter the AI era, data processing volume is surging, and many memory challenges arise in this process, so not only performance but also capacity must increase. This is why stacking competition in the HBM market is becoming more prominent.

Samsung Electronics introduced the industry's largest capacity 36-gigabyte (GB) 12-layer HBM3E in February. With SK Hynix showing strong performance in the HBM market, Samsung is quickly launching new products to regain leadership and accelerate the competition. Recently, they also announced plans to mass-produce the HBM3E 12-layer product within the second quarter.

In response, SK Hynix revised its HBM roadmap schedule this month. They plan to advance the mass production of the HBM3E 12-layer product, originally scheduled for next year, to the third quarter of this year. They have also concretized plans to provide product samples to customers as early as this month.

[Image source=Yonhap News]

The semiconductor industry expects to see the 6th generation HBM4 stacked with 16 layers after next year. As competition in the HBM market intensifies and product release cycles accelerate, it is anticipated that HBMs with higher layer counts will be released soon.

As HBM generations evolve and the number of layers increases, the company that achieves higher technological completeness is likely to take the crown in the market. The industry is paying close attention to the results of the differences in HBM manufacturing methods between Samsung Electronics and SK Hynix during this process.

HBM undergoes a silicon through-via (TSV) process, where thousands of tiny holes are drilled into the chips to connect them electrically during the stacking process. Samsung Electronics manufactures products using the 'TC-NCF' method, which inserts a thin non-conductive film (NCF) between chips and presses them with heat. SK Hynix, on the other hand, uses the 'MR-MUF' method, which applies heat to the chips and injects a liquid protective material between them to solidify.

The market evaluates that SK Hynix has improved HBM yield and product competitiveness through the MR-MUF manufacturing method. Samsung Electronics expresses confidence, stating that as the number of HBM layers increases, bending issues arise, so their manufacturing method has significant advantages. SK Hynix claims that the MR-MUF technology is suitable for high-layer stacking and has announced plans to introduce 16-layer HBM4 using this manufacturing method.

In the mid to long term, both companies are likely to adopt a new manufacturing method called 'hybrid bonding.' Hybrid bonding eliminates bumps (conductive protrusions) between chips and bonds them directly to allow electrical conduction. This method is necessary as the number of HBM layers increases, but it is technically challenging, so related research is actively underway. This is why there is high interest in the future competition in the industry that will unfold alongside the implementation of hybrid bonding.

Editor's NoteSemiconductors, often called the rice of modern industry. Although we hear the term every day, it is hard to explain. Peace & Chips will make the complex concepts of semiconductors and the overall industry flow easy to understand. Just place your spoon and enjoy.