Samsung Captures Both Size and Process with 3nm GAA... 17 Years to the Summit (Comprehensive)

Technical Concepts and Development History

Next-Generation 'Gate-All-Around' Technology
'Channel' Carrying Current Inside Transistor
Enclosed by 'Gates' on All Four Sides

Faster Data Processing and Higher Power Efficiency
Compared to Existing 'FinFET' Enclosing Three Sides

Key figures from the Foundry Business Division, Semiconductor Research Center, and Global Manufacturing & Infrastructure Headquarters, who participated in Samsung Electronics' 3-nanometer foundry mass production, are celebrating the 3-nanometer foundry mass production by holding up three fingers. (Photo by Samsung Electronics)

[Asia Economy Reporter Moon Chaeseok] Samsung Electronics' semiconductor, based on the gate-all-around (GAA) technology applied with the 3nm (nanometer) process that entered mass production from the 30th, is characterized by enhanced performance and reduced power consumption compared to semiconductors made with the existing 7nm FinFET process.

One nanometer is 'one billionth of a meter,' representing a length about one hundred thousandth the thickness of a human hair. The 3nm refers to the linewidth of the electrical circuits that can be drawn on the semiconductor being 3 nanometers, making it a next-generation semiconductor core technology that can significantly reduce the linewidth compared to the current cutting-edge 4nm semiconductor process.

It is not only about size innovation. Samsung has also developed next-generation GAA process technology that surrounds the 'channel,' through which current flows, with the 'gate' that controls the current.

Semiconductors are made up of transistors, gates, channels, and more. To place many semiconductor chips on a limited silicon wafer, the size of transistors must be reduced. Power consumption must be minimized to reduce heat generation and extend battery life.

The next-generation GAA technology developed by Samsung this time surrounds all four sides of the transistor's 'channel' with the 'gate.' This allows a larger gate area compared to the existing FinFET, which only wraps three sides. It overcomes the performance degradation of transistors caused by process miniaturization and improves data processing speed and power efficiency.

The shape was also made 'thin and wide.' The wire-shaped channel structure was implemented in a thin paper-like 'nanosheet' form. Samsung independently established the 'MBCFET' process using this form. They also performed joint design-technology co-optimization (DTCO) for the 3nm design process applying this nanosheet GAA structure. Combining these, Samsung Electronics' 3nm GAA first-generation process is expected to improve performance by 23%, reduce power consumption by 45%, and decrease area by 16% compared to the existing 5nm process. With the second-generation GAA process, performance improvement of 30%, power reduction of 50%, and area reduction of 35% are achievable.

Samsung collaborated with partners such as Synopsys and Cadence during chip design and verification. They plan to strengthen the system by providing semiconductor design infrastructure and services based on the 3nm process to partners so that customers can quickly enhance product completeness.

With this, Samsung can advance ahead of major competitors like TSMC in both 'size (3nm) + process (GAA).' It took 17 years to reach this point. Samsung Electronics, which entered the foundry business in 2005, began a super-gap technology competition by succeeding in the world's first 32nm process in 2011.

In 2017, Samsung developed the world's first 7nm process based on extreme ultraviolet (EUV) technology and started mass production in 2018. In 2019, it also succeeded in developing the EUV-based 5nm process. Most of Samsung's developments were world firsts. This was the reason they could confidently present the brand of 'super-gap management.'

After entering the foundry business, Samsung Electronics invested six full years to mass-produce the industry's first 32nm HKMG process. Then, after another four years of investment, they developed the FinFET process. The linewidth, which was 32nm, was reduced by more than half to 14nm. Of course, this is based on the 'mass production timing.' FinFET was also an innovative technology at the time of its first mass production because it allowed the gate and channel to meet on three sides.

Nevertheless, due to explosive global semiconductor demand, limitations in foundry companies' design and CPU manufacturing capabilities, and other reasons, the competition to improve process levels never ended.

On this day, Samsung became the first in the world to reach the 3nm+GAA milestone. According to plans, the size can be reduced to 2nm by the first half of 2025. Of course, the GAA process will be applied, moving to '2nm GAA.' According to the announcement, Intel will reach this milestone in the second half of 2024, and TSMC in the first half of 2025. However, Intel will remain on the FinFET process for two years, and TSMC for three years. In other words, by settling on 3nm GAA, Samsung has gained at least a '2 to 3-year' lead. After 17 years of painstaking effort, Samsung has been able to widen the gap with the world's second-tier competitors to 2 to 3 years.

Samsung Electronics plans to maximize yield (the ratio of qualified products) to calm market concerns and maintain the 'super-gap' in the speed of next technology development.