Stacking and Bonding... The Future of Semiconductor Competitiveness Depends on 'Packaging' [Juhyung Lim's Tech Talk]

Packaging, the post-process in semiconductors
Noted as a new breakthrough to elevate performance
Apple's new computer chip advances through packaging
Other semiconductor companies also unveil packaging technologies
Samsung, TSMC, Intel, etc., fiercely compete to attract packaging customers

Packaging is a post-process task that involves packaging completed semiconductors to protect the internal circuits. / Photo by Samsung Electronics official website capture

[Asia Economy Reporter Lim Juhyung] Semiconductors require ultra-fine processes at the nanometer (nm) scale, which is 100,000 times smaller than the thickness of a single hair strand. Although semiconductors are known for their extreme fine processing, the 'packaging' process is also crucial to complete a semiconductor. Commonly called packaging, this post-process involves encasing the semiconductor's internal circuits to prevent damage and connecting electrical wires to the outside. However, packaging should not be underestimated as a simple finishing technique. Recently, as semiconductor fine process technology has reached its limits, packaging is regarded as a new breakthrough that can advance computer chip performance to the next level.

◆Global Semiconductor Giants Intensify Packaging Competition

According to a recent business report from Samsung Electronics, the country's largest company, a 'Test & Package (TP) Center' was newly established within the Global Manufacturing & Infrastructure division of Samsung's Device Solutions (DS) sector. The TP Center manages the facilities, environment, and infrastructure necessary for semiconductor manufacturing and focuses on developing packaging technology.

Samsung is a company that operates a foundry business, producing semiconductors directly from designs received from semiconductor design companies. The recent strengthening of the packaging division appears aimed at securing future packaging technologies in advance and gaining a competitive edge over other foundry companies.

Samsung is not alone in accelerating packaging technology development. Intel invested $3.5 billion (approximately 4.27 trillion KRW) last year to build a new semiconductor packaging facility in New Mexico, USA, which is scheduled to begin operations in the second half of this year.

TSMC, the world's number one foundry company, invested a staggering $15 billion (approximately 18.31 trillion KRW) solely in packaging processes last year. According to the U.S. financial media Bloomberg, TSMC plans to establish close cooperative relationships with Japanese companies, traditional leaders in packaging technology.

◆Apple M1 Ultra Maximizes Performance with UltraFusion Packaging

Packaging is a post-process that involves encasing the finished semiconductor and connecting electrical wires. Since it is not directly related to the semiconductor manufacturing process, it is often considered a less important task unrelated to computer chip performance.

However, semiconductor companies have recently focused on packaging as a means to elevate computer chip performance. Packaging has enabled processes such as stacking new chips on top of semiconductors to create '3D' structures or connecting additional semiconductors side-by-side to enhance overall performance.

A representative example of performance improvement through packaging is Apple's new system-on-chip (SoC), the 'M1 Ultra.' Unveiled on the 9th (local time), the M1 Ultra is set to be installed in Apple's new computers and is the largest chip ever in both size and performance.

(From left) Apple Silicon's M1, M1 Pro, M1 Max, M1 Ultra. The Ultra computer chip is made by connecting two M1 Max chips into one. / Photo by Apple

How was Apple able to create such a chip? Comparing the M1 Ultra with other M1 chips reveals the secret. The M1 Ultra is exactly twice the size of the previous generation M1 Max because it is a chip formed by connecting two M1 Max chips. This connection method was realized through a packaging technology Apple calls 'UltraFusion.'

Connecting chip to chip to form a single SoC is by no means an easy task. The process requires meticulous attention to details such as power, heat dissipation, and bandwidth per second to ensure that software recognizes the chips as one.

However, once this method is successfully implemented, companies can reap enormous benefits. First, there is no need to redesign the new chip from scratch, saving research costs, and production is easier since existing chips can continue to be manufactured.

◆Fine Process Approaches Limits... Can Packaging Become a New Breakthrough?

Packaging technology that connects chip to chip is still a relatively new field. So far, only a few companies have released chips made through such processes.

Another packaging example is the '3D V-Cache' introduced by the American semiconductor company AMD. It is a version that enhances performance by 'stacking' additional V-Cache on top of the existing CPU semiconductor substrate.

Meanwhile, the UK startup and AI semiconductor design company Graphcore attracted industry attention by successfully implementing the world's first 'Wafer on Wafer (WoW)' packaging process, which stacks one substrate on top of another.

Graphcore designs AI-dedicated chips called 'Intelligent Processing Units.' The company achieved a remarkable feat by packaging an additional power supply substrate on top of its existing second-generation chip, boosting performance by 40% while reducing power consumption by 16%.

Companies are focusing on semiconductor packaging because of the limits of fine processing. Currently, most of the latest microprocessors are made using 7nm processes, and cutting-edge chips like Apple's 'M1' series are produced with 5nm processes. Samsung Electronics, TSMC, and others are investing massive capital to realize mass production technology for 3nm chips.

3D V-cache packaging (top) by American semiconductor design company 'AMD' and wafer-on-wafer (WoW) packaging process concept by British AI semiconductor specialist 'Graphcore'. Both companies chose 'vertical' packaging, which stacks new components on top of the chip, unlike Apple's M1 Ultra. / Photo by AMD, Graphcore

As the nm number decreases, the circuits inside the semiconductor become finer, allowing more transistors to be integrated, which increases performance. However, as fine processing approaches 1nm, mass production difficulty increases, and costs rise exponentially. Moreover, as semiconductor processes near the 1nm level, transistors shrink to nearly atomic size, where electrons flowing through circuits can suddenly quantum tunnel to other locations, causing a risk of sharp efficiency drops.

Consequently, semiconductor companies are seeking breakthroughs in packaging. If satisfactory performance improvements can be achieved simply by stacking another semiconductor on top of or beside an existing one, the burden of competing in fine processing can be significantly reduced.

Of course, packaging processes are by no means simple. In the case of Graphcore, which realized the WoW process, it reportedly conducted nearly 18 months of joint research with TSMC to complete the 'single-layer stacking' process of stacking one chip on another.

Simon Knowles, Graphcore's Chief Technology Officer, said, "We have closely collaborated with TSMC for nearly 18 months since 2020 to complete the WoW process," adding, "Other companies attempting to create new chips using our method will need to invest a considerable amount of time in research and development."

In other words, realizing complex packaging processes requires joint efforts from design and manufacturing companies, and the accumulated know-how during this process cannot be easily copied by others. This is why semiconductor manufacturers like Samsung Electronics, TSMC, and Intel are striving to attract packaging market customers as quickly as possible.