[Peace&Chips] The Unknown World of '1 Nano'... Foundry Decimal Point Competition

TSMC to Achieve 1.6nm in 2026
Intel, the Follower, Races to 1.8nm

Intensifying Fractional Competition in 1nm Transition
Focus Needed on Performance and Yield Over Numbers

Samsung Electronics' 3-nanometer foundry mass-produced in 2022.

Recently, competition in the foundry (semiconductor contract manufacturing) industry has become fierce down to decimal points. Following the 3-nanometer (nm; one billionth of a meter) and 2-nanometer eras, the 1-nanometer era is expected to arrive, with companies competing to secure technological leadership even by adding decimal points.

TSMC of Taiwan and Samsung Electronics, the world's top two foundry market players, have both announced plans to mass-produce 1.4-nanometer processes by 2027. In this context, Intel has ignited the industry's technology competition by announcing it will start mass production of the 18A (approximately 1.8-nanometer) process within this year. As a latecomer that re-entered the foundry business in 2021 after previously exiting, Intel is accelerating its pace to catch up with the leading companies.

In the foundry business, reducing nanometers is the biggest technological challenge. Nanometers refer to the line width of electronic circuits on semiconductor chips. The term originates from the Greek word 'nanos,' meaning dwarf, reflecting the extremely small scale. Since 1 nanometer is about one hundred thousandth the thickness of an adult human hair, it is hard to grasp just how minuscule it is.

Foundry companies improve semiconductor performance by reducing nanometers. The narrower the line width, the faster the processing speed and the lower the power consumption. Reducing line width also allows more circuits to be drawn on the wafer (a silicon material disc that forms the basis for semiconductor chips), thereby improving productivity. Developing technology to achieve finer nanometer scales is the destiny of the foundry industry.

However, as the industry enters the single-digit nanometer era, technological development is becoming increasingly difficult. The required technological level has risen as the process has shrunk from 7 nanometers to 5, 4, and 3 nanometers. Moving beyond the current latest 3-nanometer process to the upcoming 2-nanometer and 1-nanometer eras will inevitably make technology implementation much more challenging.

Professor Kim Jeong-ho of the Department of Electrical and Electronic Engineering at the Korea Advanced Institute of Science and Technology (KAIST) said, "1 nanometer is 10 angstroms (?; 1 ? = one ten-billionth of a meter), and since an angstrom is at the atomic scale, 1 nanometer corresponds to about 10 atoms," adding, "It is a very difficult level of technology that goes beyond electronics into the realm of quantum mechanics."

Consequently, the foundry industry has announced plans to implement various decimal point processes during the transitional period toward 1 nanometer rather than jumping directly from 2 nanometers to 1 nanometer. TSMC also revealed last week that it will produce semiconductors using the A16 (1.6-nanometer) process in the second half of 2026, prior to mass production of the 1.4-nanometer process in 2027. This is the first time TSMC has mentioned the 1.6-nanometer process, drawing significant attention both inside and outside the industry.

Within the industry, as decimal point competition unfolds in the 1-nanometer range, it is evaluated that rather than simple numerical comparisons, the key factors determining competitiveness among companies will be whether performance appropriate to the process level is achieved and how much the yield (the ratio of good products among finished products) is improved.

There is also a forecast that implementing technology beyond 1 nanometer will not happen in the short term. Attempts to enhance semiconductor performance by combining multiple semiconductors through packaging or new stacking technologies are expected to increase.

Kim Hyung-jun, head of the Next-Generation Intelligent Semiconductor Business Group and emeritus professor at Seoul National University, said, "It is physically impossible for nanometers to reach zero," adding, "Recently, much research has been conducted on CFET (Complementary Field-Effect Transistor) technology, which stacks N-type and P-type transistors vertically?previously placed horizontally?to reduce area while increasing integration density."

Editor's NoteSemiconductors, often called the rice of modern industry. Although we hear the term daily, it is hard to explain. Peace & Chips will make the complex concepts and overall flow of the semiconductor industry easy to understand. Just bring your spoon.