Fine Process Roadmap 'Squeaks'... What Is Happening to Foundry No.1 TSMC?

TSMC Delays 3nm Mass Production Again Due to Process Complexity
2025 2nm Mass Production Plan Uncertain
Investment Scale Also Reduced by 10%

[Asia Economy Reporter Han Yeju] A warning light has been lit on the mass production roadmap of TSMC, the number one foundry (semiconductor contract manufacturing) company, due to increasing production difficulties as it advances into leading-edge processes. Amid difficulties in securing yield (the proportion of good products in production) for the 3nanometer (nm; 1 nanometer is one billionth of a meter) process, there are even interpretations that TSMC is considering uncertainties regarding the introduction of new technologies and the timing of adopting the 2-nanometer process.

According to investment information firm Seeking Alpha and the semiconductor industry on the 20th, TSMC is expected to begin mass production of the 3-nanometer process by the end of the fourth quarter this year. Initially, TSMC planned to operate the 3-nanometer production line in Taiwan starting February this year and mass-produce semiconductors using 3-nanometer technology for clients such as Intel and Apple from July. However, after facing difficulties in securing yield, the mass production schedule was postponed to the end of September and has been delayed once again, making disruptions to future development schedules inevitable. It is known that TSMC is currently keeping several foundry customers on the 5-nanometer process or expanding the application of the 4-nanometer versions N4, N4P, and N4X processes.

The exact reason why TSMC is experiencing yield issues with the 3-nanometer process has not been disclosed. However, the industry believes that considering the difficulty of processes below 5 nanometers, which involve over 3,000 steps, TSMC is struggling with process development. In fact, compared to the previous generation 5-nanometer process, the 3-nanometer process increases the density of integrated devices by 50%, but requires higher costs and more advanced process technology.

The problem is that TSMC’s next-generation process mass production plans are also likely to face successive setbacks. In the foundry roadmap announced in the first half of this year, TSMC revealed plans to mass-produce the second-generation 3-nanometer process (N3E), which improves performance, power, and density, in the second half of next year, followed by sequential releases of improved 3-nanometer versions such as N3P, N3X, and N3S, and then to start mass production of the 2-nanometer process in 2025. It also announced plans to mass-produce 1.4-nanometer chips in 2027?2028.

However, since the 3-nanometer process yield has not met internal standards, even introducing the various derivative 3-nanometer semiconductor processes sequentially has become difficult. TSMC has not disclosed detailed figures regarding performance improvements as the process advances, so the intervals at which the five types of 3-nanometer derivative processes will be introduced remain uncertain. It appears natural that the introduction of the next-generation 2-nanometer process will be delayed.

An anonymous semiconductor industry official said, "TSMC prepared five derivative processes in case the 3-nanometer process technology does not meet customer expectations, but it is struggling even to get the first step right," adding, "It is increasingly likely that major customers will apply the existing 5-nanometer process to new products launching next year."

Questions about technological capability have also been raised. Digitimes expressed concerns that TSMC, which still uses the FinFET structure compared to Samsung Electronics’ Gate-All-Around (GAA) technology, may fall behind in semiconductor performance and production volume. While FinFET offers better power efficiency and integration than the previous planar FET (PlanarFET), it has limitations in finely controlling current flow compared to the next-generation GAA technology. TSMC plans to apply GAA technology starting from the 2-nanometer process.

Reducing investment scale amid the 'semiconductor cold wave' is also expected to have a negative impact. TSMC has invested enormous amounts in developing the 3-nanometer process, with the industry estimating investments of around $15 billion (approximately 61.5 trillion KRW) since 2020. However, TSMC cut its annual investment budget by at least 10% this year. In July, it had forecast capital expenditures (capex) of $40?44 billion but reportedly reduced this to about $36 billion (approximately 51.4 trillion KRW). Increasing the share of leading-edge processes requires investments worth several trillion won. Ultimately, cost increases due to inflation and difficulties in forecasting demand in upstream industries seem unavoidable.

The foundry industry is paying attention to the possibility of market shifts as technological competition enters the 3-nanometer process, where process difficulty increases. Compared to processes of 5 nanometers and above, production volume is expected to decrease significantly due to yield issues, and prices will rise, intensifying the tendency of foundry companies to be selective with customers. The market regards the 3-nanometer process as a potential 'game changer' in the foundry market. Market research firm Omdia predicts that from 2024, the 3-nanometer process (16.1%) will surpass the 5-nanometer process (15.9%) in market share.