[Samsung's First 3nm Mass Production] 'World's First' Every Time in Development and Mass Production

Technical Concepts and Development History

Next-Generation 'Gate-All-Around' Technology
'Channel' Carrying Current Inside Transistor
Surrounded on Four Sides by 'Gate'

Faster Data Processing and Higher Power Efficiency
Compared to Existing 'FinFET' Surrounding Three Sides

Executives of Samsung Electronics Foundry Division. From the left, Senior Manager Jeong Won-cheol, Vice President Koo Ja-heum, and Senior Manager Kang Sang-beom are showing a 3nm wafer at the 3nm mass production line in the Hwaseong Campus. (Photo by Samsung Electronics)

[Asia Economy Reporter Moon Chaeseok] Samsung Electronics' semiconductor, based on gate-all-around (GAA) technology applied with the 3nm (nanometer) process that entered mass production from the 30th, is characterized by enhanced performance and reduced power consumption compared to semiconductors made with the existing 7nm FinFET process.

One nanometer is 'one billionth of a meter,' representing about one hundred-thousandth the thickness of a human hair. The 3nm refers to the line width of the electric circuits that can be drawn on the semiconductor being 3 nanometers, making it a next-generation semiconductor core technology that can significantly reduce the circuit line width compared to the current cutting-edge 4nm semiconductor process.

It is not just about size innovation. Samsung has also developed next-generation GAA process technology that surrounds the 'channel,' through which current flows, with the 'gate' that controls the current.

Semiconductors are made up of transistors, gates, channels, and so on. To place many semiconductor chips on a limited silicon wafer, the size of transistors must be reduced. Power consumption must be minimized to reduce heat generation and extend battery life.

The next-generation GAA technology developed by Samsung this time makes the 'gate' surround all four sides of the 'channel' inside the transistor. This allows a larger gate area compared to the existing FinFET, which only wraps three sides. This overcomes the performance degradation of transistors due to process miniaturization and improves data processing speed and power efficiency.

The shape was also made 'thin and wide.' The wire-shaped channel structure was implemented in a thin paper-like 'nanosheet' form. Samsung independently established the 'MBCFET' process made in this form. They also performed joint optimization of 3nm design process technology (DTCO) applying this nanosheet GAA structure. Combining these, Samsung Electronics' 3nm GAA 1st generation process is expected to improve performance by 23%, reduce power consumption by 45%, and decrease area by 16% compared to the existing 5nm process. With the 2nd generation GAA process, performance improvement of 30%, power reduction of 50%, and area reduction of 35% can be realized.

Samsung collaborated with partners such as Synopsys and Cadence during chip design and verification. They plan to strengthen the system by providing semiconductor design infrastructure and services based on the 3nm process to partners so that customers can quickly enhance product completeness.

Thus, Samsung has been able to get ahead of major competitors like TSMC in both 'size (3nm) + process (GAA).' It took 17 years to reach this point. Samsung Electronics, which entered the foundry business in 2005, began a super-gap technology competition by succeeding in the world's first 32nm process in 2011.

In 2017, Samsung developed the world's first 7nm process based on extreme ultraviolet (EUV) technology and started mass production in 2018. In 2019, it also succeeded in developing the EUV-based 5nm process. Most of Samsung's developments were world firsts. This was the reason they could confidently present the brand of 'super-gap management.'

After entering the foundry business, Samsung Electronics invested six full years to mass-produce the industry's first 32nm HKMG process. Then, after another four years of investment, they developed the FinFET process. The line width, which was 32nm in size, was reduced by more than half to 14nm. Of course, this is based on the 'mass production timing.' FinFET was also an innovative technology at the time of its first mass production because the gate and channel met on three sides.

Nevertheless, due to explosive global semiconductor demand, limitations in foundry companies' design and CPU manufacturing capabilities, and other reasons, the competition to improve process levels never ended. On this day, Samsung became the first in the world to settle on the 3nm + GAA summit.